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| author | Corentin Labbe <clabbe.montjoie@gmail.com> | 2017-06-05 21:21:26 +0200 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2017-06-06 20:06:30 +0200 |
| commit | 1dcd0095019aca7533eaeed9475d995a4eb30137 (patch) | |
| tree | a459e27d8f46b30a27b043c1811ab9b4e851ee82 /arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | |
| parent | 378af662f8d4a30ceddae1e5c5d1acb6da7f9796 (diff) | |
| download | lwn-1dcd0095019aca7533eaeed9475d995a4eb30137.tar.gz lwn-1dcd0095019aca7533eaeed9475d995a4eb30137.zip | |
ARM: sun8i: orangepi-plus: Enable dwmac-sun8i
The dwmac-sun8i hardware is present on the Orange PI plus.
It uses an external PHY rtl8211e via RGMII.
This patch create the needed regulator, emac and phy nodes.
Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts')
| -rw-r--r-- | arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts | 32 |
1 files changed, 32 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts index 8c40ab7bfa72..331ed683ac62 100644 --- a/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts +++ b/arch/arm/boot/dts/sun8i-h3-orangepi-plus.dts @@ -47,6 +47,20 @@ model = "Xunlong Orange Pi Plus / Plus 2"; compatible = "xunlong,orangepi-plus", "allwinner,sun8i-h3"; + aliases { + ethernet0 = &emac; + }; + + reg_gmac_3v3: gmac-3v3 { + compatible = "regulator-fixed"; + regulator-name = "gmac-3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + startup-delay-us = <100000>; + enable-active-high; + gpio = <&pio 3 6 GPIO_ACTIVE_HIGH>; + }; + reg_usb3_vbus: usb3-vbus { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -64,6 +78,24 @@ status = "okay"; }; +&emac { + pinctrl-names = "default"; + pinctrl-0 = <&emac_rgmii_pins>; + phy-supply = <®_gmac_3v3>; + phy-handle = <&ext_rgmii_phy>; + phy-mode = "rgmii"; + + allwinner,leds-active-low; + status = "okay"; +}; + +&mdio { + ext_rgmii_phy: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + &mmc2 { pinctrl-names = "default"; pinctrl-0 = <&mmc2_8bit_pins>; |