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| author | Dinh Nguyen <dinguyen@opensource.altera.com> | 2016-10-19 10:56:33 -0500 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@kernel.org> | 2016-11-08 15:40:34 -0600 |
| commit | 5d662bf15dcb35c79c8b80db468e1cb4a43cc066 (patch) | |
| tree | 04673f589f7d420c337df4dc2f2d9b48e17cde7b /arch/arm/boot/dts/socfpga_arria10.dtsi | |
| parent | e8f0ff58330b76342359986a0321520106e80ad3 (diff) | |
| download | lwn-5d662bf15dcb35c79c8b80db468e1cb4a43cc066.tar.gz lwn-5d662bf15dcb35c79c8b80db468e1cb4a43cc066.zip | |
ARM: dts: socfpga: Add QSPI node for the Arria10
Add the QSPI device node for Arria10 SOC.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_arria10.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_arria10.dtsi | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 1149216c78c5..551c636a4f01 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -675,6 +675,20 @@ }; }; + qspi: spi@ff809000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff809000 0x100>, + <0xffa00000 0x100000>; + interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + clocks = <&qspi_clk>; + status = "disabled"; + }; + rst: rstmgr@ffd05000 { #reset-cells = <1>; compatible = "altr,rst-mgr"; |