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authorAndy Yan <andy.yan@rock-chips.com>2017-08-14 16:41:57 +0800
committerHeiko Stuebner <heiko@sntech.de>2017-08-14 15:33:22 +0200
commit0e6ff96faa2e5cc0c4d22118c35d558a61c6f7bc (patch)
tree2549b8c04e6bc5fee9267ba928276ace7f7a1029 /arch/arm/boot/dts/rv1108.dtsi
parent5584b967da664661f9f6f2adef817aaffa324041 (diff)
downloadlwn-0e6ff96faa2e5cc0c4d22118c35d558a61c6f7bc.tar.gz
lwn-0e6ff96faa2e5cc0c4d22118c35d558a61c6f7bc.zip
ARM: dts: rockchip: add saradc support for rv1108
Add saradc device tree node for rv1108 soc Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rv1108.dtsi')
-rw-r--r--arch/arm/boot/dts/rv1108.dtsi11
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rv1108.dtsi b/arch/arm/boot/dts/rv1108.dtsi
index 991b35d87c52..3259335a86c0 100644
--- a/arch/arm/boot/dts/rv1108.dtsi
+++ b/arch/arm/boot/dts/rv1108.dtsi
@@ -214,6 +214,17 @@
status = "disabled";
};
+ adc: adc@1038c000 {
+ compatible = "rockchip,rv1108-saradc", "rockchip,rk3399-saradc";
+ reg = <0x1038c000 0x100>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ #io-channel-cells = <1>;
+ clock-frequency = <1000000>;
+ clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
+ clock-names = "saradc", "apb_pclk";
+ status = "disabled";
+ };
+
i2c0: i2c@20000000 {
compatible = "rockchip,rv1108-i2c";
reg = <0x20000000 0x1000>;