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authorViresh Kumar <viresh.kumar@linaro.org>2018-05-25 16:01:56 +0530
committerHeiko Stuebner <heiko@sntech.de>2018-06-18 12:31:52 +0200
commitf999d76a0011abfd814c8513a5e60a7eb9b9dac0 (patch)
tree8be790b1faaa46909648e5a7fd697459b448fd11 /arch/arm/boot/dts/rk3288.dtsi
parentce76de984649bf85c81ee437eea282d10ba0dbb3 (diff)
downloadlwn-f999d76a0011abfd814c8513a5e60a7eb9b9dac0.tar.gz
lwn-f999d76a0011abfd814c8513a5e60a7eb9b9dac0.zip
ARM: dts: rockchip: Add missing cooling device properties for CPUs on rk3288
The cooling device properties, like "#cooling-cells" and "dynamic-power-coefficient", should either be present for all the CPUs of a cluster or none. If these are present only for a subset of CPUs of a cluster then things will start falling apart as soon as the CPUs are brought online in a different order. For example, this will happen because the operating system looks for such properties in the CPU node it is trying to bring up, so that it can register a cooling device. Add such missing properties. Fix other missing properties (clocks, OPP, clock latency) as well to make it all work. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> [follow conversion to operating-points-v2] Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288.dtsi')
-rw-r--r--arch/arm/boot/dts/rk3288.dtsi12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi
index 7094f95b967f..0840ffb3205c 100644
--- a/arch/arm/boot/dts/rk3288.dtsi
+++ b/arch/arm/boot/dts/rk3288.dtsi
@@ -70,18 +70,30 @@
compatible = "arm,cortex-a12";
reg = <0x501>;
resets = <&cru SRST_CORE1>;
+ operating-points = <&cpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
};
cpu2: cpu@502 {
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x502>;
resets = <&cru SRST_CORE2>;
+ operating-points = <&cpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
};
cpu3: cpu@503 {
device_type = "cpu";
compatible = "arm,cortex-a12";
reg = <0x503>;
resets = <&cru SRST_CORE3>;
+ operating-points = <&cpu_opp_table>;
+ #cooling-cells = <2>; /* min followed by max */
+ clock-latency = <40000>;
+ clocks = <&cru ARMCLK>;
};
};