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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2017-03-06 17:40:39 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2017-03-07 07:44:39 +0100 |
| commit | d492909c84b895564d7ac413546ae988945c68db (patch) | |
| tree | 9b5cf25cad988558dd7956aa5f287e18d67319c1 /arch/arm/boot/dts/r8a7790.dtsi | |
| parent | 51c00a9f730dd27da23e9dec593c22c0f9f5a1b1 (diff) | |
| download | lwn-d492909c84b895564d7ac413546ae988945c68db.tar.gz lwn-d492909c84b895564d7ac413546ae988945c68db.zip | |
ARM: dts: r8a7790: Remove unit-addresses and regs from integrated caches
The Cortex-A15/A7 cache controllers are integrated controllers, and thus
the device nodes representing them should not have unit-addresses or reg
properties.
Fixes: 2c3de36700d4f3a5 ("ARM: dts: r8a7790: Fix W=1 dtc warnings")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7790.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7790.dtsi | 6 |
1 files changed, 2 insertions, 4 deletions
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 6d10450de6d7..20cf191e0852 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -129,17 +129,15 @@ next-level-cache = <&L2_CA7>; }; - L2_CA15: cache-controller@0 { + L2_CA15: cache-controller-0 { compatible = "cache"; - reg = <0>; power-domains = <&sysc R8A7790_PD_CA15_SCU>; cache-unified; cache-level = <2>; }; - L2_CA7: cache-controller@100 { + L2_CA7: cache-controller-1 { compatible = "cache"; - reg = <0x100>; power-domains = <&sysc R8A7790_PD_CA7_SCU>; cache-unified; cache-level = <2>; |