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| author | Biju Das <biju.das@bp.renesas.com> | 2018-11-30 15:26:28 +0000 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-12-04 06:05:22 -0800 |
| commit | ce28396b7a8621e048cfb8d002bc869b428a905e (patch) | |
| tree | 5a671cd0150040eda4b82b283824df8f8b18eec0 /arch/arm/boot/dts/r8a7744.dtsi | |
| parent | f9a3d5f23b6c8e4029a3474945971477d1f9365a (diff) | |
| download | lwn-ce28396b7a8621e048cfb8d002bc869b428a905e.tar.gz lwn-ce28396b7a8621e048cfb8d002bc869b428a905e.zip | |
ARM: dts: r8a7744: USB 2.0 host support
Describe internal PCI bridge devices, USB phy device and
link PCI USB devices to USB phy.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7744.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7744.dtsi | 77 |
1 files changed, 72 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 3f7674b2aac5..1d4cb5e447cd 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -454,8 +454,25 @@ }; usbphy: usb-phy@e6590100 { + compatible = "renesas,usb-phy-r8a7744", + "renesas,rcar-gen2-usb-phy"; reg = <0 0xe6590100 0 0x100>; - /* placeholder */ + #address-cells = <1>; + #size-cells = <0>; + clocks = <&cpg CPG_MOD 704>; + clock-names = "usbhs"; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 704>; + status = "disabled"; + + usb0: usb-channel@0 { + reg = <0>; + #phy-cells = <1>; + }; + usb2: usb-channel@2 { + reg = <2>; + #phy-cells = <1>; + }; }; dmac0: dma-controller@e6700000 { @@ -847,23 +864,73 @@ }; pci0: pci@ee090000 { - reg = <0 0xee090000 0 0xc00>; + compatible = "renesas,pci-r8a7744", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee090000 0 0xc00>, + <0 0xee080000 0 0x1100>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; bus-range = <0 0>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - /* placeholder */ + ranges = <0x02000000 0 0xee080000 0 0xee080000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x800 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x1000 0 0 0 0>; + phys = <&usb0 0>; + phy-names = "usb"; + }; }; pci1: pci@ee0d0000 { - reg = <0 0xee0d0000 0 0xc00>; + compatible = "renesas,pci-r8a7744", + "renesas,pci-rcar-gen2"; + device_type = "pci"; + reg = <0 0xee0d0000 0 0xc00>, + <0 0xee0c0000 0 0x1100>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 703>; + power-domains = <&sysc R8A7744_PD_ALWAYS_ON>; + resets = <&cpg 703>; + status = "disabled"; bus-range = <1 1>; #address-cells = <3>; #size-cells = <2>; #interrupt-cells = <1>; - /* placeholder */ + ranges = <0x02000000 0 0xee0c0000 0 0xee0c0000 0 0x00010000>; + interrupt-map-mask = <0xff00 0 0 0x7>; + interrupt-map = <0x0000 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x0800 0 0 1 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH + 0x1000 0 0 2 &gic GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + + usb@1,0 { + reg = <0x10800 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; + + usb@2,0 { + reg = <0x11000 0 0 0 0>; + phys = <&usb2 0>; + phy-names = "usb"; + }; }; sdhi0: sd@ee100000 { |