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| author | Biju Das <biju.das@bp.renesas.com> | 2018-11-28 16:38:29 +0000 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-12-04 06:21:26 -0800 |
| commit | 350ae49b97c4612002e253a311f5070680509373 (patch) | |
| tree | 4be93c4cd3afbf40fc7ac8a9d6fd8ed6519c8f26 /arch/arm/boot/dts/r8a7744.dtsi | |
| parent | eddcbe813dd3c8247840859bf4d04b3423d35f8f (diff) | |
| download | lwn-350ae49b97c4612002e253a311f5070680509373.tar.gz lwn-350ae49b97c4612002e253a311f5070680509373.zip | |
ARM: dts: r8a7744: Add IPMMU DT nodes
Add the six IPMMU instances found in the r8a7744 to DT with a disabled
status.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7744.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7744.dtsi | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index be84400c08ad..06952f5a1e9f 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -328,6 +328,64 @@ #thermal-sensor-cells = <0>; }; + ipmmu_sy0: mmu@e6280000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6280000 0 0x1000>; + interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_sy1: mmu@e6290000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6290000 0 0x1000>; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_ds: mmu@e6740000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xe6740000 0 0x1000>; + interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mp: mmu@ec680000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xec680000 0 0x1000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_mx: mmu@fe951000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xfe951000 0 0x1000>; + interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + + ipmmu_gp: mmu@e62a0000 { + compatible = "renesas,ipmmu-r8a7744", + "renesas,ipmmu-vmsa"; + reg = <0 0xe62a0000 0 0x1000>; + interrupts = <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH>; + #iommu-cells = <1>; + status = "disabled"; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; |