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| author | Tony Lindgren <tony@atomide.com> | 2016-09-09 14:04:28 -0700 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2016-09-13 14:57:12 -0700 |
| commit | 952a5db0c0f8ddf9776c84e818769f5c6e97ec38 (patch) | |
| tree | d2ae8b32f9868830ba0d7a2330498e161f62b28f /arch/arm/boot/dts/omap5.dtsi | |
| parent | 08f9268b2a2e16ad89187a49ac06bfc7e1dc36a6 (diff) | |
| download | lwn-952a5db0c0f8ddf9776c84e818769f5c6e97ec38.tar.gz lwn-952a5db0c0f8ddf9776c84e818769f5c6e97ec38.zip | |
ARM: dts: Configure omap5 OTG ID pin
The ID pin GPIO comes from the PMIC. Let's configure it as a GPIO
for the driver to use, and also make sure the PMIC GPIO pin muxing
is correct. The PMIC pad1 and 2 values for omap5-uevm and igepv5 are
0x5a and 0x1b, we only need to clear bit 2 in pad1 register to make
the ID pin GPIO work.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/omap5.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/omap5.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi index 71a8f5492c8b..c2ef1285a3dd 100644 --- a/arch/arm/boot/dts/omap5.dtsi +++ b/arch/arm/boot/dts/omap5.dtsi @@ -863,7 +863,7 @@ #size-cells = <1>; utmi-mode = <2>; ranges; - dwc3@4a030000 { + dwc3: dwc3@4a030000 { compatible = "snps,dwc3"; reg = <0x4a030000 0x10000>; interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, |