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| author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2018-07-21 21:05:53 +0200 |
|---|---|---|
| committer | Kevin Hilman <khilman@baylibre.com> | 2018-09-04 14:05:00 -0700 |
| commit | f31094fe8c16fbd2ca47921acf93b744b045aace (patch) | |
| tree | e2571ae327c664f2f0545c21c79f98baea68f8d4 /arch/arm/boot/dts/meson8b.dtsi | |
| parent | f7f9da89bc4f61e33f7b9f5c75c4efdc1f0455d8 (diff) | |
| download | lwn-f31094fe8c16fbd2ca47921acf93b744b045aace.tar.gz lwn-f31094fe8c16fbd2ca47921acf93b744b045aace.zip | |
ARM: dts: meson8b: fix the clock controller register size
The clock controller registers are not 0x460 wide because the reset
controller starts at CBUS 0x4404. This currently overlaps with the
clock controller (which is at CBUS 0x4000).
There is no public documentation available on the actual size of the
clock controller's register area (also called "HHI"). However, in
Amlogic's GPL kernel sources the last "HHI" register is
HHI_HDMI_PHY_CNTL2 at CBUS + 0x43a8. 0x400 was chosen because that size
doesn't seem unlikely.
Fixes: 4a69fcd3a10803 ("ARM: meson: Add DTS for Odroid-C1 and Tronfy MXQ boards")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm/boot/dts/meson8b.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/meson8b.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index 08f7f6be7254..f77e419c1c65 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -163,7 +163,7 @@ #clock-cells = <1>; #reset-cells = <1>; compatible = "amlogic,meson8b-clkc"; - reg = <0x8000 0x4>, <0x4000 0x460>; + reg = <0x8000 0x4>, <0x4000 0x400>; }; reset: reset-controller@4404 { |