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author | Martin Blumenstingl <martin.blumenstingl@googlemail.com> | 2019-01-18 23:52:21 +0100 |
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committer | Kevin Hilman <khilman@baylibre.com> | 2019-02-11 12:52:25 -0800 |
commit | b6db3936f2833c9f27aa9d868bb7bb6e87401b40 (patch) | |
tree | fca37c1249b265ef053f120d6ee508bd4a77ae8e /arch/arm/boot/dts/meson8.dtsi | |
parent | 29f0023d01f063feacfc404f0446905aee4f82ee (diff) | |
download | lwn-b6db3936f2833c9f27aa9d868bb7bb6e87401b40.tar.gz lwn-b6db3936f2833c9f27aa9d868bb7bb6e87401b40.zip |
ARM: dts: meson: switch the clock controller to the HHI register area
The clock controller on Meson8/Meson8m2 and Meson8b is part of a
register region called "HHI". This register area contains more
functionality than just a clock controller:
- the clock controller
- some reset controller bits
- temperature sensor calibration data (on Meson8b and Meson8m2 only)
- HDMI controller
Allow access to this HHI register area as "system controller". Also
migrate the Meson8 and Meson8b clock controllers to this new node.
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Diffstat (limited to 'arch/arm/boot/dts/meson8.dtsi')
-rw-r--r-- | arch/arm/boot/dts/meson8.dtsi | 15 |
1 files changed, 8 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 1ea5a36c5040..66b167537aaa 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -327,13 +327,6 @@ }; &cbus { - clkc: clock-controller@4000 { - #clock-cells = <1>; - #reset-cells = <1>; - compatible = "amlogic,meson8-clkc"; - reg = <0x8000 0x4>, <0x4000 0x400>; - }; - reset: reset-controller@4404 { compatible = "amlogic,meson8b-reset"; reg = <0x4404 0x9c>; @@ -468,6 +461,14 @@ status = "okay"; }; +&hhi { + clkc: clock-controller { + compatible = "amlogic,meson8-clkc"; + #clock-cells = <1>; + #reset-cells = <1>; + }; +}; + &hwrng { compatible = "amlogic,meson8-rng", "amlogic,meson-rng"; clocks = <&clkc CLKID_RNG0>; |