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| author | Patrick Havelange <patrick.havelange@essensium.com> | 2018-12-11 16:48:34 +0100 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-01-10 15:03:24 +0800 |
| commit | cd8281acdf91379dfa001e2e523ca192360c1d02 (patch) | |
| tree | 3a263bdb880c4072fe8cad8496d5a6521dfcc043 /arch/arm/boot/dts/ls1021a.dtsi | |
| parent | 02f95c355122d5a93d2663df867aa8e2bde5480a (diff) | |
| download | lwn-cd8281acdf91379dfa001e2e523ca192360c1d02.tar.gz lwn-cd8281acdf91379dfa001e2e523ca192360c1d02.zip | |
ARM: dts: ls1021a: Add memory controller
The LS1021A has a memory controller that supports EDAC. This commit
adds an entry for it.
Signed-off-by: Patrick Havelange <patrick.havelange@essensium.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/ls1021a.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/ls1021a.dtsi | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index ed0941292172..6df6a291f4d0 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -125,6 +125,13 @@ interrupt-parent = <&gic>; ranges; + ddr: memory-controller@1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; + big-endian; + }; + gic: interrupt-controller@1400000 { compatible = "arm,gic-400", "arm,cortex-a7-gic"; #interrupt-cells = <3>; |