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| author | Jagan Teki <jagan@amarulasolutions.com> | 2017-06-15 17:33:39 +0530 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2017-07-16 09:42:12 +0800 |
| commit | 4cfad559da170508f96879bc12d039765befcf3e (patch) | |
| tree | 7312e321d38ad826f9c550bed6d746098cad3de7 /arch/arm/boot/dts/imx6ul-isiot.dtsi | |
| parent | ddab367d4cf6608ba84aa57583d52ffa8ee878d2 (diff) | |
| download | lwn-4cfad559da170508f96879bc12d039765befcf3e.tar.gz lwn-4cfad559da170508f96879bc12d039765befcf3e.zip | |
ARM: dts: imx6ul-isiot: Add FEC node support
Add support for fec1 node on Engicam Is.IoT variant boards.
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx6ul-isiot.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/imx6ul-isiot.dtsi | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx6ul-isiot.dtsi b/arch/arm/boot/dts/imx6ul-isiot.dtsi index e2dacdcef39a..950fb28b630a 100644 --- a/arch/arm/boot/dts/imx6ul-isiot.dtsi +++ b/arch/arm/boot/dts/imx6ul-isiot.dtsi @@ -115,6 +115,24 @@ }; }; +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet1>; + phy-mode = "rmii"; + phy-handle = <ðphy0>; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + &i2c1 { clock-frequency = <100000>; pinctrl-names = "default"; @@ -227,6 +245,21 @@ }; &iomuxc { + pinctrl_enet1: enet1grp { + fsl,pins = < + MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 + MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 |