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| author | Marek Vasut <marex@denx.de> | 2019-05-16 00:46:01 +0200 |
|---|---|---|
| committer | Shawn Guo <shawnguo@kernel.org> | 2019-05-20 09:09:24 +0800 |
| commit | 7870756fe4564bca438e8dfb06fb78075ffc82b1 (patch) | |
| tree | 0496d05555eb2ff1ae6b36413771ee950e4a1bcf /arch/arm/boot/dts/imx53-m53menlo.dts | |
| parent | 34c486a2ce668df0829ddf98b5cf7b1913daefab (diff) | |
| download | lwn-7870756fe4564bca438e8dfb06fb78075ffc82b1.tar.gz lwn-7870756fe4564bca438e8dfb06fb78075ffc82b1.zip | |
ARM: dts: imx53: Update pinmux settings on M53Menlo
Update pinmux settings according to hardware team input.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/imx53-m53menlo.dts')
| -rw-r--r-- | arch/arm/boot/dts/imx53-m53menlo.dts | 87 |
1 files changed, 49 insertions, 38 deletions
diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts index a106233d1651..55c122a64ef0 100644 --- a/arch/arm/boot/dts/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/imx53-m53menlo.dts @@ -235,27 +235,31 @@ imx53-m53evk { hoggrp { fsl,pins = < - MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 - MX53_PAD_EIM_EB3__GPIO2_31 0x1d5 - MX53_PAD_PATA_DA_0__GPIO7_6 0x1d5 - MX53_PAD_GPIO_19__CCM_CLKO 0x1d5 - MX53_PAD_CSI0_MCLK__CCM_CSI0_MCLK 0x1d5 - MX53_PAD_CSI0_DAT4__GPIO5_22 0x1d5 - MX53_PAD_CSI0_DAT5__GPIO5_23 0x1d5 - MX53_PAD_CSI0_DAT6__GPIO5_24 0x1d5 - MX53_PAD_CSI0_DAT7__GPIO5_25 0x1d5 - MX53_PAD_CSI0_DAT8__GPIO5_26 0x1d5 - MX53_PAD_CSI0_DAT9__GPIO5_27 0x1d5 - MX53_PAD_CSI0_DAT10__GPIO5_28 0x1d5 - MX53_PAD_CSI0_DAT11__GPIO5_29 0x1d5 - MX53_PAD_CSI0_DAT14__GPIO6_0 0x1d5 + MX53_PAD_GPIO_19__CCM_CLKO 0x1e4 + MX53_PAD_CSI0_DATA_EN__GPIO5_20 0x1e4 + MX53_PAD_CSI0_DAT4__GPIO5_22 0x1e4 + MX53_PAD_CSI0_DAT5__GPIO5_23 0x1c4 + MX53_PAD_CSI0_DAT6__GPIO5_24 0x1e4 + MX53_PAD_CSI0_DAT7__GPIO5_25 0x1e4 + MX53_PAD_CSI0_DAT8__GPIO5_26 0x1e4 + MX53_PAD_CSI0_DAT9__GPIO5_27 0x1c4 + MX53_PAD_CSI0_DAT10__GPIO5_28 0x1e4 + MX53_PAD_CSI0_DAT11__GPIO5_29 0x1e4 + MX53_PAD_PATA_DATA11__GPIO2_11 0x1e4 + MX53_PAD_EIM_D24__GPIO3_24 0x1e4 + MX53_PAD_EIM_D25__GPIO3_25 0x1e4 + MX53_PAD_EIM_D29__GPIO3_29 0x1e4 + MX53_PAD_CSI0_PIXCLK__GPIO5_18 0x1e4 + MX53_PAD_CSI0_VSYNC__GPIO5_21 0x1e4 + MX53_PAD_CSI0_DAT18__GPIO6_4 0x1c4 + MX53_PAD_PATA_DATA8__GPIO2_8 0x1e4 >; }; pinctrl_led: ledgrp { fsl,pins = < - MX53_PAD_CSI0_DAT15__GPIO6_1 0x1d5 - MX53_PAD_CSI0_DAT16__GPIO6_2 0x1d5 + MX53_PAD_CSI0_DAT15__GPIO6_1 0x1c4 + MX53_PAD_CSI0_DAT16__GPIO6_2 0x1c4 >; }; @@ -274,49 +278,56 @@ pinctrl_can2: can2grp { fsl,pins = < - MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1c4 + MX53_PAD_KEY_COL4__CAN2_TXCAN 0x1e4 MX53_PAD_KEY_ROW4__CAN2_RXCAN 0x1c4 >; }; pinctrl_display_gpio: display-gpiogrp { fsl,pins = < - MX53_PAD_CSI0_DAT12__GPIO5_30 0x1d5 /* Reset */ - MX53_PAD_CSI0_DAT13__GPIO5_31 0x1d5 /* Interrupt */ + MX53_PAD_CSI0_DAT12__GPIO5_30 0x1c4 /* Reset */ + MX53_PAD_CSI0_MCLK__GPIO5_19 0x1e4 /* Int-K */ + MX53_PAD_CSI0_DAT13__GPIO5_31 0x1c4 /* Int-I */ + + MX53_PAD_CSI0_DAT14__GPIO6_0 0x1c4 /* Power down */ >; }; pinctrl_edt_ft5x06: edt-ft5x06grp { fsl,pins = < - MX53_PAD_PATA_DATA9__GPIO2_9 0x1d5 /* Reset */ - MX53_PAD_CSI0_DAT19__GPIO6_5 0x1d5 /* Interrupt */ - MX53_PAD_PATA_DATA10__GPIO2_10 0x1d5 /* Wake */ + MX53_PAD_PATA_DATA9__GPIO2_9 0x1e4 /* Reset */ + MX53_PAD_CSI0_DAT19__GPIO6_5 0x1c4 /* Interrupt */ + MX53_PAD_PATA_DATA10__GPIO2_10 0x1e4 /* Wake */ >; }; pinctrl_esdhc1: esdhc1grp { fsl,pins = < - MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 - MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 - MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 - MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 - MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 - MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1e4 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1e4 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1e4 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1e4 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1e4 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1e4 + MX53_PAD_GPIO_1__GPIO1_1 0x1c4 + MX53_PAD_GPIO_9__GPIO1_9 0x1e4 >; }; pinctrl_fec: fecgrp { fsl,pins = < - MX53_PAD_FEC_MDC__FEC_MDC 0x4 - MX53_PAD_FEC_MDIO__FEC_MDIO 0x1fc - MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x180 - MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x180 - MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x180 - MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x180 - MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x180 - MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x4 - MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x4 - MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x4 + MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 + MX53_PAD_PATA_DA_1__GPIO7_7 0x1e4 + MX53_PAD_EIM_EB3__GPIO2_31 0x1e4 >; }; |