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authorAlexander Shiyan <shc_work@mail.ru>2013-08-21 11:28:23 +0400
committerShawn Guo <shawn.guo@linaro.org>2013-09-26 13:01:30 +0800
commit727b8124f5c714c687d9aabbdfe7ca9593db735f (patch)
treeb77bfbb11c1975226f270ff8630afd5bf3d6f731 /arch/arm/boot/dts/imx51.dtsi
parent44a26877080825ab55080ad4ff9293a728bf5a98 (diff)
downloadlwn-727b8124f5c714c687d9aabbdfe7ca9593db735f.tar.gz
lwn-727b8124f5c714c687d9aabbdfe7ca9593db735f.zip
ARM: dts: i.MX51: Separate TXD/RXD and RTS/CTS pinmux entries for UARTs
RTS/CTS pins can be used for different purposes, so create separate definitions for these pins. Signed-off-by: Alexander Shiyan <shc_work@mail.ru> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/imx51.dtsi')
-rw-r--r--arch/arm/boot/dts/imx51.dtsi10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi
index 54cee6517902..1db97deb64b6 100644
--- a/arch/arm/boot/dts/imx51.dtsi
+++ b/arch/arm/boot/dts/imx51.dtsi
@@ -747,6 +747,11 @@
fsl,pins = <
MX51_PAD_UART1_RXD__UART1_RXD 0x1c5
MX51_PAD_UART1_TXD__UART1_TXD 0x1c5
+ >;
+ };
+
+ pinctrl_uart1_rtscts_1: uart1rtscts-1 {
+ fsl,pins = <
MX51_PAD_UART1_RTS__UART1_RTS 0x1c5
MX51_PAD_UART1_CTS__UART1_CTS 0x1c5
>;
@@ -767,6 +772,11 @@
fsl,pins = <
MX51_PAD_EIM_D25__UART3_RXD 0x1c5
MX51_PAD_EIM_D26__UART3_TXD 0x1c5
+ >;
+ };
+
+ pinctrl_uart3_rtscts_1: uart3rtscts-1 {
+ fsl,pins = <
MX51_PAD_EIM_D27__UART3_RTS 0x1c5
MX51_PAD_EIM_D24__UART3_CTS 0x1c5
>;