diff options
| author | Alim Akhtar <alim.akhtar@samsung.com> | 2015-10-13 04:32:53 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene@kernel.org> | 2015-10-13 04:40:27 +0900 |
| commit | b8bb9baad27e455c467e8fac47eebadbe765c18f (patch) | |
| tree | 2baa2f188c7dda37189541bc508257305e117efb /arch/arm/boot/dts/exynos5420-peach-pit.dts | |
| parent | 51a6256b00008a3c520f6f31bcd62cd15cb05960 (diff) | |
| download | lwn-b8bb9baad27e455c467e8fac47eebadbe765c18f.tar.gz lwn-b8bb9baad27e455c467e8fac47eebadbe765c18f.zip | |
ARM: dts: Fix audio card detection on Peach boards
Since commit 2fad972d45c4 ("ARM: dts: Add mclk entry for Peach boards"),
sound card detection is broken on peach boards and gives below errors:
[ 3.630457] max98090 7-0010: MAX98091 REVID=0x51
[ 3.634233] max98090 7-0010: use default 2.8v micbias
[ 3.640985] snow-audio sound: HiFi <-> 3830000.i2s mapping ok
[ 3.645307] max98090 7-0010: Invalid master clock frequency
[ 3.650824] snow-audio sound: ASoC: Peach-Pi-I2S-MAX98091 late_probe() failed: -22
[ 3.658914] snow-audio sound: snd_soc_register_card failed (-22)
[ 3.664366] snow-audio: probe of sound failed with error -22
This patch adds missing assigned-clocks and assigned-clock-parents for
pmu_system_controller node which is used as "mclk" for audio codec.
Fixes: 2fad972d45c4 ("ARM: dts: Add mclk entry for Peach boards")
Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Cc: <stable@vger.kernel.org>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos5420-peach-pit.dts')
| -rw-r--r-- | arch/arm/boot/dts/exynos5420-peach-pit.dts | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5420-peach-pit.dts b/arch/arm/boot/dts/exynos5420-peach-pit.dts index 8f4d76c5e11c..1b95da79293c 100644 --- a/arch/arm/boot/dts/exynos5420-peach-pit.dts +++ b/arch/arm/boot/dts/exynos5420-peach-pit.dts @@ -915,6 +915,11 @@ }; }; +&pmu_system_controller { + assigned-clocks = <&pmu_system_controller 0>; + assigned-clock-parents = <&clock CLK_FIN_PLL>; +}; + &rtc { status = "okay"; clocks = <&clock CLK_RTC>, <&max77802 MAX77802_CLK_32K_AP>; |