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authorDavid Lechner <david@lechnology.com>2016-10-31 15:47:19 -0500
committerSekhar Nori <nsekhar@ti.com>2016-11-01 15:11:10 +0530
commit1b499f255589204466d8f8ab26e6b577d7b5c88f (patch)
tree8185d984c02bb90030e63523c28b1b4a9c2dcc13 /arch/arm/boot/dts/da850.dtsi
parentb5028b287242b346ed396f14edb2e6156a368951 (diff)
downloadlwn-1b499f255589204466d8f8ab26e6b577d7b5c88f.tar.gz
lwn-1b499f255589204466d8f8ab26e6b577d7b5c88f.zip
ARM: dts: da850: Add cfgchip syscon node
Add a syscon node for the SoC CFGCHIPn registers. It includes a child node for the USB PHY that is part of this range of registers. Signed-off-by: David Lechner <david@lechnology.com> [nsekhar@ti.com: drop OF_DEV_AUXDATA() addition] Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'arch/arm/boot/dts/da850.dtsi')
-rw-r--r--arch/arm/boot/dts/da850.dtsi10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/da850.dtsi b/arch/arm/boot/dts/da850.dtsi
index 4c836133a183..2534aab851e1 100644
--- a/arch/arm/boot/dts/da850.dtsi
+++ b/arch/arm/boot/dts/da850.dtsi
@@ -209,6 +209,16 @@
};
};
+ cfgchip: chip-controller@1417c {
+ compatible = "ti,da830-cfgchip", "syscon", "simple-mfd";
+ reg = <0x1417c 0x14>;
+
+ usb_phy: usb-phy {
+ compatible = "ti,da830-usb-phy";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
+ };
edma0: edma@0 {
compatible = "ti,edma3-tpcc";
/* eDMA3 CC0: 0x01c0 0000 - 0x01c0 7fff */