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| author | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2016-11-05 19:03:50 +0100 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@free-electrons.com> | 2016-11-19 09:16:35 +0100 |
| commit | 007d05d898050ffc70fd2737896528c5069f7269 (patch) | |
| tree | 18ebf273fc48790e82a3e1ab14cb02a9bfaffe6c /arch/arm/boot/dts/armada-xp-synology-ds414.dts | |
| parent | 1fc2129553c5a387be786c4b302e3a253a7d01a8 (diff) | |
| download | lwn-007d05d898050ffc70fd2737896528c5069f7269.tar.gz lwn-007d05d898050ffc70fd2737896528c5069f7269.zip | |
ARM: dts: armada-xp: Fixup pcie DT warnings
PCIe has a range property, so the unit name should contain an address.
Take the opportunity to use the node label instead of the full name.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-xp-synology-ds414.dts')
| -rw-r--r-- | arch/arm/boot/dts/armada-xp-synology-ds414.dts | 45 |
1 files changed, 23 insertions, 22 deletions
diff --git a/arch/arm/boot/dts/armada-xp-synology-ds414.dts b/arch/arm/boot/dts/armada-xp-synology-ds414.dts index 189ec7f4667c..d5630a7b4b18 100644 --- a/arch/arm/boot/dts/armada-xp-synology-ds414.dts +++ b/arch/arm/boot/dts/armada-xp-synology-ds414.dts @@ -81,28 +81,6 @@ MBUS_ID(0x09, 0x09) 0 0 0xf1100000 0x10000 MBUS_ID(0x09, 0x05) 0 0 0xf1110000 0x10000>; - pcie-controller { - status = "okay"; - - /* - * Connected to Marvell 88SX7042 SATA-II controller - * handling the four disks. - */ - pcie@1,0 { - /* Port 0, Lane 0 */ - status = "okay"; - }; - - /* - * Connected to EtronTech EJ168A XHCI controller - * providing the two rear USB 3.0 ports. - */ - pcie@5,0 { - /* Port 1, Lane 0 */ - status = "okay"; - }; - }; - internal-regs { /* RTC is provided by Seiko S-35390A below */ @@ -230,6 +208,29 @@ }; }; +&pciec { + status = "okay"; + + /* + * Connected to Marvell 88SX7042 SATA-II controller + * handling the four disks. + */ + pcie@1,0 { + /* Port 0, Lane 0 */ + status = "okay"; + }; + + /* + * Connected to EtronTech EJ168A XHCI controller + * providing the two rear USB 3.0 ports. + */ + pcie@5,0 { + /* Port 1, Lane 0 */ + status = "okay"; + }; +}; + + &mdio { phy0: ethernet-phy@0 { /* Marvell 88E1512 */ reg = <0>; |