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| author | Russell King <rmk+kernel@armlinux.org.uk> | 2018-02-27 16:01:57 +0000 |
|---|---|---|
| committer | Gregory CLEMENT <gregory.clement@bootlin.com> | 2018-03-05 17:33:42 +0100 |
| commit | a83aeb3836b1cd65770b20eafefbef7467972fa2 (patch) | |
| tree | 548590248138484d17ebf38dc0f8cff93fdd9445 /arch/arm/boot/dts/armada-388-clearfog.dtsi | |
| parent | e662e70fa41985d258ba82f47bb248d2433c52e0 (diff) | |
| download | lwn-a83aeb3836b1cd65770b20eafefbef7467972fa2.tar.gz lwn-a83aeb3836b1cd65770b20eafefbef7467972fa2.zip | |
ARM: dts: armada388-clearfog: increase speed of i2c0 to 400kHz
All the devices on I2C0 support fast mode, so increase the bus speed
to match. The Armada 388 is known to have a timing issue when in
standard mode, which we believe causes the ficticious device at 0x64
to appear.
[gregory.clement@bootlin.com: Note that since the commit fbffee74986c
("ARM: dts: Fix I2C repeated start issue on Armada-38x") in 4.14, the
timing issue is managed for the Armada 38x SoCs.]
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Diffstat (limited to 'arch/arm/boot/dts/armada-388-clearfog.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/armada-388-clearfog.dtsi | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/arch/arm/boot/dts/armada-388-clearfog.dtsi b/arch/arm/boot/dts/armada-388-clearfog.dtsi index 68acfc968706..0e3b1f140e6d 100644 --- a/arch/arm/boot/dts/armada-388-clearfog.dtsi +++ b/arch/arm/boot/dts/armada-388-clearfog.dtsi @@ -143,8 +143,7 @@ }; &i2c0 { - /* Is there anything on this? */ - clock-frequency = <100000>; + clock-frequency = <400000>; pinctrl-0 = <&i2c0_pins>; pinctrl-names = "default"; status = "okay"; @@ -239,13 +238,11 @@ }; }; - /* The MCP3021 is 100kHz clock only */ + /* The MCP3021 supports standard and fast modes */ mikrobus_adc: mcp3021@4c { compatible = "microchip,mcp3021"; reg = <0x4c>; }; - - /* Also something at 0x64 */ }; &i2c1 { |