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| author | Poddar, Sourav <sourav.poddar@ti.com> | 2014-04-29 19:45:46 +0530 |
|---|---|---|
| committer | Tero Kristo <t-kristo@ti.com> | 2014-05-23 11:50:36 +0300 |
| commit | 4da1c67719f612af9f3ba2c804efa9d2452bae76 (patch) | |
| tree | cafe0589364333ecd611fc8896bac1aac70be574 /arch/arm/boot/dts/am43xx-clocks.dtsi | |
| parent | 9e100ebafb913c7bedfbfc0e0e1f97b3e43d8a4c (diff) | |
| download | lwn-4da1c67719f612af9f3ba2c804efa9d2452bae76.tar.gz lwn-4da1c67719f612af9f3ba2c804efa9d2452bae76.zip | |
ARM: dts: am43x-clock: add tbclk data for ehrpwm
We need "tbclk" clock data for the functioning of ehrpwm
module. Hence, populating the required clock information
in clock dts file.
Signed-off-by: Sourav Poddar <sourav.poddar@ti.com>
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Diffstat (limited to 'arch/arm/boot/dts/am43xx-clocks.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/am43xx-clocks.dtsi | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/am43xx-clocks.dtsi b/arch/arm/boot/dts/am43xx-clocks.dtsi index 1d9b6bba7af1..3ad99a64dd16 100644 --- a/arch/arm/boot/dts/am43xx-clocks.dtsi +++ b/arch/arm/boot/dts/am43xx-clocks.dtsi @@ -87,6 +87,54 @@ clock-mult = <1>; clock-div = <1>; }; + + ehrpwm0_tbclk: ehrpwm0_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <0>; + reg = <0x0664>; + }; + + ehrpwm1_tbclk: ehrpwm1_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <1>; + reg = <0x0664>; + }; + + ehrpwm2_tbclk: ehrpwm2_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <2>; + reg = <0x0664>; + }; + + ehrpwm3_tbclk: ehrpwm3_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <4>; + reg = <0x0664>; + }; + + ehrpwm4_tbclk: ehrpwm4_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <5>; + reg = <0x0664>; + }; + + ehrpwm5_tbclk: ehrpwm5_tbclk { + #clock-cells = <0>; + compatible = "ti,gate-clock"; + clocks = <&dpll_per_m2_ck>; + ti,bit-shift = <6>; + reg = <0x0664>; + }; }; &prcm_clocks { clk_32768_ck: clk_32768_ck { |