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| author | Roger Quadros <rogerq@ti.com> | 2016-04-07 13:25:39 +0300 |
|---|---|---|
| committer | Tony Lindgren <tony@atomide.com> | 2016-04-12 14:32:02 -0700 |
| commit | 63015d73f345a9196e910b84c3f329a22556bcf4 (patch) | |
| tree | d8a7007a063a6cb34c3a46fefa8cd5fccc476123 /arch/arm/boot/dts/am335x-chilisom.dtsi | |
| parent | 99a4101182d6107af869fb6d41cb375c717c66ad (diff) | |
| download | lwn-63015d73f345a9196e910b84c3f329a22556bcf4.tar.gz lwn-63015d73f345a9196e910b84c3f329a22556bcf4.zip | |
ARM: dts: am335x: Provide NAND ready pin
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
For NAND we don't use GPMC wait pin monitoring but
get the NAND Ready/Busy# status using GPIOlib.
GPMC driver provides the WAIT0 pin status over GPIOlib.
Read speed increases from 7869 KiB/ to 8875 KiB/s
and write speed was unchanged at 5100 KiB/s.
Measured using mtd_speedtest.ko on am335x-evm.
Cc: Teresa Remmet <t.remmet@phytec.de>
Cc: Ilya Ledvich <ilya@compulab.co.il>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Cc: Rostislav Lisovy <lisovy@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/am335x-chilisom.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/am335x-chilisom.dtsi | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/am335x-chilisom.dtsi b/arch/arm/boot/dts/am335x-chilisom.dtsi index 95461a28bc98..e48c28236baa 100644 --- a/arch/arm/boot/dts/am335x-chilisom.dtsi +++ b/arch/arm/boot/dts/am335x-chilisom.dtsi @@ -214,6 +214,7 @@ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ + rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; |