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| author | Will Deacon <will.deacon@arm.com> | 2012-04-20 17:20:08 +0100 |
|---|---|---|
| committer | Ben Hutchings <ben@decadent.org.uk> | 2012-05-11 13:14:44 +0100 |
| commit | 28bd5ddf286b858b8148c3de5854cbc00e701229 (patch) | |
| tree | 4bff338a576f0b7d689b1efaa75322bb532a95dd /arch/arm/Kconfig | |
| parent | fd81c41a855b671788991872ab0a0dcdcc6ee1fa (diff) | |
| download | lwn-28bd5ddf286b858b8148c3de5854cbc00e701229.tar.gz lwn-28bd5ddf286b858b8148c3de5854cbc00e701229.zip | |
ARM: 7396/1: errata: only handle ARM erratum #326103 on affected cores
commit f0c4b8d653f5ee091fb8d4d02ed7eaad397491bb upstream.
Erratum #326103 ("FSR write bit incorrect on a SWP to read-only memory")
only affects the ARM 1136 core prior to r1p0. The workaround
disassembles the faulting instruction to determine whether it was a read
or write access on all v6 cores.
An issue has been reported on the ARM 11MPCore whereby loading the
faulting instruction may happen in parallel with that page being
unmapped, resulting in a deadlock due to the lack of TLB broadcasting
in hardware:
http://lists.infradead.org/pipermail/linux-arm-kernel/2012-March/091561.html
This patch limits the workaround so that it is only used on affected
cores, which are known to be UP only. Other v6 cores can rely on the
FSR to indicate the access type correctly.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
Diffstat (limited to 'arch/arm/Kconfig')
| -rw-r--r-- | arch/arm/Kconfig | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index ab3740ec79a3..ef642a01eacb 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1155,6 +1155,15 @@ if !MMU source "arch/arm/Kconfig-nommu" endif +config ARM_ERRATA_326103 + bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory" + depends on CPU_V6 + help + Executing a SWP instruction to read-only memory does not set bit 11 + of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to + treat the access as a read, preventing a COW from occurring and + causing the faulting task to livelock. + config ARM_ERRATA_411920 bool "ARM errata: Invalidation of the Instruction Cache operation can fail" depends on CPU_V6 || CPU_V6K |