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authorVijay Purushothaman <vijay.a.purushothaman@intel.com>2012-09-27 19:13:04 +0530
committerDaniel Vetter <daniel.vetter@ffwll.ch>2012-09-28 16:49:53 +0200
commit74a4dd2e4594804ffeb04b3e60ff4cfbf6b8ce10 (patch)
tree5b15df8a3458116a8111f4913d8eb4a9826e8078 /REPORTING-BUGS
parentb56747aace48a269fefa7d337963cbae6e95b0a0 (diff)
downloadlwn-74a4dd2e4594804ffeb04b3e60ff4cfbf6b8ce10.tar.gz
lwn-74a4dd2e4594804ffeb04b3e60ff4cfbf6b8ce10.zip
drm/i915: Program correct m n tu register for Valleyview
m n tu register offset has changed in Valleyview. Also fixed DP limit frequencies. Signed-off-by: Vijay Purushothaman <vijay.a.purushothaman@intel.com> Signed-off-by: Ben Widawsky <benjamin.widawsky@intel.com> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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