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| author | Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> | 2016-06-13 00:06:52 +0300 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-06-16 09:25:20 +0900 |
| commit | 7c4163aae3d8e5b9bd72508f542a44d707f308b5 (patch) | |
| tree | d32e29063e7fdd412ca3780f499f86c1f29b0d0c /Makefile | |
| parent | 5258bb5d980024dae22f4256329caec4fe5e98b3 (diff) | |
| download | lwn-7c4163aae3d8e5b9bd72508f542a44d707f308b5.tar.gz lwn-7c4163aae3d8e5b9bd72508f542a44d707f308b5.zip | |
ARM: dts: r8a7792: initial SoC device tree
The initial R8A7792 SoC device tree including CPU cores, GIC, timer, SYSC,
and the required clock descriptions.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'Makefile')
0 files changed, 0 insertions, 0 deletions