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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2023-06-30 09:37:26 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2023-06-30 09:37:26 -0700 |
| commit | 533925cb760431cb496a8c965cfd765a1a21d37e (patch) | |
| tree | c43ac0f7d69f9b9a3f1e18509a9a75654cbb3607 /MAINTAINERS | |
| parent | d8b0bd57c2d68eb500f356f0f9228e6183da94ae (diff) | |
| parent | 488833ccdcac118da16701f4ee0673b20ba47fe3 (diff) | |
| download | lwn-533925cb760431cb496a8c965cfd765a1a21d37e.tar.gz lwn-533925cb760431cb496a8c965cfd765a1a21d37e.zip | |
Merge tag 'riscv-for-linus-6.5-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux
Pull RISC-V updates from Palmer Dabbelt:
- Support for ACPI
- Various cleanups to the ISA string parsing, including making them
case-insensitive
- Support for the vector extension
- Support for independent irq/softirq stacks
- Our CPU DT binding now has "unevaluatedProperties: false"
* tag 'riscv-for-linus-6.5-mw1' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (78 commits)
riscv: hibernate: remove WARN_ON in save_processor_state
dt-bindings: riscv: cpus: switch to unevaluatedProperties: false
dt-bindings: riscv: cpus: add a ref the common cpu schema
riscv: stack: Add config of thread stack size
riscv: stack: Support HAVE_SOFTIRQ_ON_OWN_STACK
riscv: stack: Support HAVE_IRQ_EXIT_ON_IRQ_STACK
RISC-V: always report presence of extensions formerly part of the base ISA
dt-bindings: riscv: explicitly mention assumption of Zicntr & Zihpm support
RISC-V: remove decrement/increment dance in ISA string parser
RISC-V: rework comments in ISA string parser
RISC-V: validate riscv,isa at boot, not during ISA string parsing
RISC-V: split early & late of_node to hartid mapping
RISC-V: simplify register width check in ISA string parsing
perf: RISC-V: Limit the number of counters returned from SBI
riscv: replace deprecated scall with ecall
riscv: uprobes: Restore thread.bad_cause
riscv: mm: try VMA lock-based page fault handling first
riscv: mm: Pre-allocate PGD entries for vmalloc/modules area
RISC-V: hwprobe: Expose Zba, Zbb, and Zbs
RISC-V: Track ISA extensions per hart
...
Diffstat (limited to 'MAINTAINERS')
| -rw-r--r-- | MAINTAINERS | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 96e4a0dd3a6f..1545c55b9173 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -406,6 +406,13 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/acpi/arm64 +ACPI FOR RISC-V (ACPI/riscv) +M: Sunil V L <sunilvl@ventanamicro.com> +L: linux-acpi@vger.kernel.org +L: linux-riscv@lists.infradead.org +S: Maintained +F: drivers/acpi/riscv/ + ACPI PCC(Platform Communication Channel) MAILBOX DRIVER M: Sudeep Holla <sudeep.holla@arm.com> L: linux-acpi@vger.kernel.org |