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| author | Bjorn Helgaas <bhelgaas@google.com> | 2024-11-25 13:40:56 -0600 |
|---|---|---|
| committer | Bjorn Helgaas <bhelgaas@google.com> | 2024-11-25 13:40:56 -0600 |
| commit | 0683141812ce93a6604c51b60101744577c65154 (patch) | |
| tree | 98c28144ea7edd80ccfe7a57b37d69ba21de559c /Documentation | |
| parent | 5cdd50dc1099983eff4e6b30cf0c290469c0d283 (diff) | |
| parent | 718c157a0b941fe2d3b4cca689148775e6ea2330 (diff) | |
| download | lwn-0683141812ce93a6604c51b60101744577c65154.tar.gz lwn-0683141812ce93a6604c51b60101744577c65154.zip | |
Merge branch 'pci/dt-bindings'
- Update mediatek-gen3 DT binding to require the exact number of clocks for
each SoC (Fei Shao)
- Add qcom SAR2130P DT binding with an additional clock (Dmitry Baryshkov)
* pci/dt-bindings:
dt-bindings: PCI: snps,dw-pcie: Drop "#interrupt-cells" from example
dt-bindings: PCI: qcom,pcie-sm8550: Add SAR2130P compatible
dt-bindings: PCI: mediatek-gen3: Allow exact number of clocks only
Diffstat (limited to 'Documentation')
3 files changed, 6 insertions, 4 deletions
diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 898c1be2d6a4..f05aab2b1add 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -149,7 +149,7 @@ allOf: then: properties: clocks: - minItems: 4 + minItems: 6 clock-names: items: @@ -178,7 +178,7 @@ allOf: then: properties: clocks: - minItems: 4 + minItems: 6 clock-names: items: @@ -207,6 +207,7 @@ allOf: properties: clocks: minItems: 4 + maxItems: 4 clock-names: items: diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml index 24cb38673581..2b5498a35dcc 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml @@ -20,6 +20,7 @@ properties: - const: qcom,pcie-sm8550 - items: - enum: + - qcom,sar2130p-pcie - qcom,pcie-sm8650 - const: qcom,pcie-sm8550 @@ -39,7 +40,7 @@ properties: clocks: minItems: 7 - maxItems: 8 + maxItems: 9 clock-names: minItems: 7 @@ -52,6 +53,7 @@ properties: - const: ddrss_sf_tbu # PCIe SF TBU clock - const: noc_aggr # Aggre NoC PCIe AXI clock - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + - const: qmip_pcie_ahb # QMIP PCIe AHB clock interrupts: minItems: 8 diff --git a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml index 548f59d76ef2..205326fb2d75 100644 --- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml @@ -230,7 +230,6 @@ examples: interrupts = <25>, <24>; interrupt-names = "msi", "hp"; - #interrupt-cells = <1>; reset-gpios = <&port0 0 1>; |