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| author | Kulkarni, Ganapatrao <Ganapatrao.Kulkarni@cavium.com> | 2018-12-06 11:51:27 +0000 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2018-12-06 12:29:47 +0000 |
| commit | d6310a3f3396e004bdb7a76787a2a3bbc643d0b7 (patch) | |
| tree | d5757f27db38310299eb834ea0c813419b818754 /Documentation/perf | |
| parent | 754a58db6a556e6e5f5e32f3e84e7d67b5bf9c8e (diff) | |
| download | lwn-d6310a3f3396e004bdb7a76787a2a3bbc643d0b7.tar.gz lwn-d6310a3f3396e004bdb7a76787a2a3bbc643d0b7.zip | |
Documentation: perf: Add documentation for ThunderX2 PMU uncore driver
The SoC has PMU support in its L3 cache controller (L3C) and in the
DDR4 Memory Controller (DMC).
Signed-off-by: Ganapatrao Kulkarni <ganapatrao.kulkarni@cavium.com>
[will: minor spelling and format fixes, dropped events list]
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/perf')
| -rw-r--r-- | Documentation/perf/thunderx2-pmu.txt | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/Documentation/perf/thunderx2-pmu.txt b/Documentation/perf/thunderx2-pmu.txt new file mode 100644 index 000000000000..dffc57143736 --- /dev/null +++ b/Documentation/perf/thunderx2-pmu.txt @@ -0,0 +1,41 @@ +Cavium ThunderX2 SoC Performance Monitoring Unit (PMU UNCORE) +============================================================= + +The ThunderX2 SoC PMU consists of independent, system-wide, per-socket +PMUs such as the Level 3 Cache (L3C) and DDR4 Memory Controller (DMC). + +The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles. +Events are counted for the default channel (i.e. channel 0) and prorated +to the total number of channels/tiles. + +The DMC and L3C support up to 4 counters. Counters are independently +programmable and can be started and stopped individually. Each counter +can be set to a different event. Counters are 32-bit and do not support +an overflow interrupt; they are read every 2 seconds. + +PMU UNCORE (perf) driver: + +The thunderx2_pmu driver registers per-socket perf PMUs for the DMC and +L3C devices. Each PMU can be used to count up to 4 events +simultaneously. The PMUs provide a description of their available events +and configuration options under sysfs, see +/sys/devices/uncore_<l3c_S/dmc_S/>; S is the socket id. + +The driver does not support sampling, therefore "perf record" will not +work. Per-task perf sessions are also not supported. + +Examples: + +# perf stat -a -e uncore_dmc_0/cnt_cycles/ sleep 1 + +# perf stat -a -e \ +uncore_dmc_0/cnt_cycles/,\ +uncore_dmc_0/data_transfers/,\ +uncore_dmc_0/read_txns/,\ +uncore_dmc_0/write_txns/ sleep 1 + +# perf stat -a -e \ +uncore_l3c_0/read_request/,\ +uncore_l3c_0/read_hit/,\ +uncore_l3c_0/inv_request/,\ +uncore_l3c_0/inv_hit/ sleep 1 |