diff options
author | Boris BREZILLON <boris.brezillon@free-electrons.com> | 2014-05-14 14:38:15 +0200 |
---|---|---|
committer | Maxime Ripard <maxime.ripard@free-electrons.com> | 2014-05-15 10:30:53 +0200 |
commit | 1e84443e69c1fdbef76fb3897294e924461a6c0a (patch) | |
tree | 7e860d74ee311041cf6230eaf7eff3a0b45b1faa /Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt | |
parent | c9eaa447e77efe77b7fa4c953bd62de8297fd6c5 (diff) | |
download | lwn-1e84443e69c1fdbef76fb3897294e924461a6c0a.tar.gz lwn-1e84443e69c1fdbef76fb3897294e924461a6c0a.zip |
reset: sunxi: document sunxi's reset controllers bindings
Add DT bindings documentation for sunxi's reset controllers.
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Diffstat (limited to 'Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt')
-rw-r--r-- | Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt new file mode 100644 index 000000000000..c8f775714887 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/allwinner,sunxi-clock-reset.txt @@ -0,0 +1,21 @@ +Allwinner sunxi Peripheral Reset Controller +=========================================== + +Please also refer to reset.txt in this directory for common reset +controller binding usage. + +Required properties: +- compatible: Should be one of the following: + "allwinner,sun6i-a31-ahb1-reset" + "allwinner,sun6i-a31-clock-reset" +- reg: should be register base and length as documented in the + datasheet +- #reset-cells: 1, see below + +example: + +ahb1_rst: reset@01c202c0 { + #reset-cells = <1>; + compatible = "allwinner,sun6i-a31-ahb1-reset"; + reg = <0x01c202c0 0xc>; +}; |