diff options
| author | Marek Behún <marek.behun@nic.cz> | 2020-04-30 10:06:22 +0200 |
|---|---|---|
| committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2020-05-18 14:40:39 +0100 |
| commit | e89897c9dec7f859a93b8364709851c3a7418ac3 (patch) | |
| tree | 790d60b3af9dacb48ef06a4cfa1a299d1673cedb /Documentation/devicetree/bindings/pci | |
| parent | 96be36dbffacea0aa9e6ec4839583e79faa141a1 (diff) | |
| download | lwn-e89897c9dec7f859a93b8364709851c3a7418ac3.tar.gz lwn-e89897c9dec7f859a93b8364709851c3a7418ac3.zip | |
dt-bindings: PCI: aardvark: Describe new properties
Document the possibility to reference a PHY and reset-gpios and to set
max-link-speed property.
Link: https://lore.kernel.org/r/20200430080625.26070-10-pali@kernel.org
Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: devicetree@vger.kernel.org
Diffstat (limited to 'Documentation/devicetree/bindings/pci')
| -rw-r--r-- | Documentation/devicetree/bindings/pci/aardvark-pci.txt | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/aardvark-pci.txt b/Documentation/devicetree/bindings/pci/aardvark-pci.txt index 310ef7145c47..2b8ca920a7fa 100644 --- a/Documentation/devicetree/bindings/pci/aardvark-pci.txt +++ b/Documentation/devicetree/bindings/pci/aardvark-pci.txt @@ -19,6 +19,9 @@ contain the following properties: - interrupt-map-mask and interrupt-map: standard PCI properties to define the mapping of the PCIe interface to interrupt numbers. - bus-range: PCI bus numbers covered + - phys: the PCIe PHY handle + - max-link-speed: see pci.txt + - reset-gpios: see pci.txt In addition, the Device Tree describing an Aardvark PCIe controller must include a sub-node that describes the legacy interrupt controller @@ -48,6 +51,7 @@ Example: <0 0 0 2 &pcie_intc 1>, <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; + phys = <&comphy1 0>; pcie_intc: interrupt-controller { interrupt-controller; #interrupt-cells = <1>; |