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| author | Niklas Cassel <cassel@kernel.org> | 2024-06-07 13:14:23 +0200 |
|---|---|---|
| committer | Krzysztof Wilczyński <kwilczynski@kernel.org> | 2024-06-21 18:48:37 +0000 |
| commit | 6f308c017c2729a5e70cf6282a74ff0f43b8e90c (patch) | |
| tree | d7cfcae6e37063babb1266155791cf57b98282f9 /Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml | |
| parent | b96353773d24359c1830a90e79b8240a2720b605 (diff) | |
| download | lwn-6f308c017c2729a5e70cf6282a74ff0f43b8e90c.tar.gz lwn-6f308c017c2729a5e70cf6282a74ff0f43b8e90c.zip | |
dt-bindings: PCI: snps,dw-pcie-ep: Add tx_int{a,b,c,d} legacy IRQs
The DWC core has four interrupt signals: tx_inta, tx_intb, tx_intc, tx_intd
that are triggered when the PCIe controller (when running in Endpoint mode)
has sent an Assert_INTA Message to the upstream device.
Some DWC controllers have these interrupt in a combined interrupt signal.
Add the description of these interrupts to the device tree binding.
Link: https://lore.kernel.org/linux-pci/20240607-rockchip-pcie-ep-v1-v5-3-0a042d6b0049@kernel.org
Signed-off-by: Niklas Cassel <cassel@kernel.org>
Signed-off-by: Krzysztof Wilczyński <kwilczynski@kernel.org>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml')
0 files changed, 0 insertions, 0 deletions