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| author | Linu Cherian <linu.cherian@cavium.com> | 2017-06-22 17:35:37 +0530 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2017-06-23 17:58:03 +0100 |
| commit | e5b829de053d9994dfc8652ce558e90e3406c578 (patch) | |
| tree | 6215ecb21bf1ebad7ff0e5a123369d1cb69d764d /Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | |
| parent | 403e8c7c5bcaff3291a2c7012fe80f707a854d10 (diff) | |
| download | lwn-e5b829de053d9994dfc8652ce558e90e3406c578.tar.gz lwn-e5b829de053d9994dfc8652ce558e90e3406c578.zip | |
iommu/arm-smmu-v3: Add workaround for Cavium ThunderX2 erratum #74
Cavium ThunderX2 SMMU implementation doesn't support page 1 register space
and PAGE0_REGS_ONLY option is enabled as an errata workaround.
This option when turned on, replaces all page 1 offsets used for
EVTQ_PROD/CONS, PRIQ_PROD/CONS register access with page 0 offsets.
SMMU resource size checks are now based on SMMU option PAGE0_REGS_ONLY,
since resource size can be either 64k/128k.
For this, arm_smmu_device_dt_probe/acpi_probe has been moved before
platform_get_resource call, so that SMMU options are set beforehand.
Signed-off-by: Linu Cherian <linu.cherian@cavium.com>
Signed-off-by: Geetha Sowjanya <geethasowjanya.akula@cavium.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt')
| -rw-r--r-- | Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt index be57550e14e4..e7855cf6038e 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt @@ -49,6 +49,12 @@ the PCIe specification. - hisilicon,broken-prefetch-cmd : Avoid sending CMD_PREFETCH_* commands to the SMMU. +- cavium,cn9900-broken-page1-regspace + : Replaces all page 1 offsets used for EVTQ_PROD/CONS, + PRIQ_PROD/CONS register access with page 0 offsets. + Set for Cavium ThunderX2 silicon that doesn't support + SMMU page1 register space. + ** Example smmu@2b400000 { |