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| author | Rohit Agarwal <quic_rohiagar@quicinc.com> | 2022-02-22 10:26:21 +0530 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-03-08 16:17:40 -0600 |
| commit | 2cabc45237659cb3b0294c8b8ae12f5fd0dad28d (patch) | |
| tree | d9af2f98e440e4eec215285ac005c8b0fbec6cb2 /Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | |
| parent | 013804a727a0482bc6661e15dfababde5f856550 (diff) | |
| download | lwn-2cabc45237659cb3b0294c8b8ae12f5fd0dad28d.tar.gz lwn-2cabc45237659cb3b0294c8b8ae12f5fd0dad28d.zip | |
dt-bindings: clock: Add A7 PLL binding for SDX65
Add information for Cortex A7 PLL clock in Qualcomm
platform SDX65.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-2-git-send-email-quic_rohiagar@quicinc.com
Diffstat (limited to 'Documentation/devicetree/bindings/clock/qcom,a7pll.yaml')
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml index 8666e995725f..0e96f693b050 100644 --- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml @@ -10,7 +10,7 @@ maintainers: - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> description: - The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high + The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high frequency clock to the CPU. properties: |