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authorDaniel Palmer <daniel@0x0f.com>2021-02-23 15:18:23 +0900
committerRomain Perier <romain.perier@gmail.com>2022-02-16 19:16:03 +0100
commitc952e5075de1f76e092bc780503ebc5cb8222a01 (patch)
treedfba76087a292a3e1e7d5ae5488c7acb7e6b4798 /Documentation/devicetree/bindings/clock/mstar,msc313-cpupll.yaml
parenta6801eecea700c9fb9a1d049375bbb4a848c8b5c (diff)
downloadlwn-c952e5075de1f76e092bc780503ebc5cb8222a01.tar.gz
lwn-c952e5075de1f76e092bc780503ebc5cb8222a01.zip
dt-bindings: clk: mstar msc313 cpupll binding description
Add a binding description for the MStar/SigmaStar CPU PLL block. Signed-off-by: Daniel Palmer <daniel@0x0f.com> Reviewed-by: Rob Herring <robh@kernel.org>
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+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/mstar,msc313-cpupll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MStar/Sigmastar MSC313 CPU PLL
+
+maintainers:
+ - Daniel Palmer <daniel@thingy.jp>
+
+description: |
+ The MStar/SigmaStar MSC313 and later ARMv7 chips have a scalable
+ PLL that can be used as the clock source for the CPU(s).
+
+properties:
+ compatible:
+ const: mstar,msc313-cpupll
+
+ "#clock-cells":
+ const: 1
+
+ clocks:
+ maxItems: 1
+
+ reg:
+ maxItems: 1
+
+required:
+ - compatible
+ - "#clock-cells"
+ - clocks
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mstar-msc313-mpll.h>
+ cpupll: cpupll@206400 {
+ compatible = "mstar,msc313-cpupll";
+ reg = <0x206400 0x200>;
+ #clock-cells = <1>;
+ clocks = <&mpll MSTAR_MSC313_MPLL_DIV2>;
+ };