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author | Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com> | 2021-12-27 14:35:47 +0100 |
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committer | Dinh Nguyen <dinguyen@kernel.org> | 2022-02-09 10:43:02 -0600 |
commit | ad7f9f3ad1bc7403d0b6d655d92fa7b4b1899629 (patch) | |
tree | 29f778eacdf3031a6828427d6c2d685e6b1735a0 /Documentation/devicetree/bindings/clock/intel,stratix10.yaml | |
parent | abca30aa14b1ec3d96547ec71d690aa1169cc4e6 (diff) | |
download | lwn-ad7f9f3ad1bc7403d0b6d655d92fa7b4b1899629.tar.gz lwn-ad7f9f3ad1bc7403d0b6d655d92fa7b4b1899629.zip |
dt-bindings: clock: intel,stratix10: convert to dtschema
Convert the Intel Stratix 10 clock controller bindings to DT schema format.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/intel,stratix10.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/clock/intel,stratix10.yaml | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/intel,stratix10.yaml b/Documentation/devicetree/bindings/clock/intel,stratix10.yaml new file mode 100644 index 000000000000..f506e3db9782 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/intel,stratix10.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/intel,stratix10.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel SoCFPGA Stratix10 platform clock controller binding + +maintainers: + - Dinh Nguyen <dinguyen@kernel.org> + +properties: + compatible: + const: intel,stratix10-clkmgr + + '#clock-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@ffd10000 { + compatible = "intel,stratix10-clkmgr"; + reg = <0xffd10000 0x1000>; + #clock-cells = <1>; + }; |