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| author | Suzuki K Poulose <suzuki.poulose@arm.com> | 2017-03-14 18:13:27 +0000 |
|---|---|---|
| committer | Catalin Marinas <catalin.marinas@arm.com> | 2017-03-20 16:30:22 +0000 |
| commit | c651aae5a7732287c1c9bc974ece4ed798780544 (patch) | |
| tree | bc3647b41e405e93747c80021850563d6a49d7db /Documentation/arm64/cpu-feature-registers.txt | |
| parent | cb567e79fa504575cb97fb2f866d2040ed1c92e7 (diff) | |
| download | lwn-c651aae5a7732287c1c9bc974ece4ed798780544.tar.gz lwn-c651aae5a7732287c1c9bc974ece4ed798780544.zip | |
arm64: v8.3: Support for weaker release consistency
ARMv8.3 adds new instructions to support Release Consistent
processor consistent (RCpc) model, which is weaker than the
RCsc model.
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64/cpu-feature-registers.txt')
| -rw-r--r-- | Documentation/arm64/cpu-feature-registers.txt | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt index 0ce0a4021aa4..d1c97f9f51cc 100644 --- a/Documentation/arm64/cpu-feature-registers.txt +++ b/Documentation/arm64/cpu-feature-registers.txt @@ -174,6 +174,8 @@ infrastructure: x--------------------------------------------------x | Name | bits | visible | |--------------------------------------------------| + | LRCPC | [23-20] | y | + |--------------------------------------------------| | FCMA | [19-16] | y | |--------------------------------------------------| | JSCVT | [15-12] | y | |