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authorDongjiu Geng <gengdongjiu@huawei.com>2017-12-13 18:13:56 +0800
committerCatalin Marinas <catalin.marinas@arm.com>2018-01-05 11:29:48 +0000
commit3b3b681097fae73b7f5dcdd42db6cfdf32943d4c (patch)
tree514122d4fd4358c7dfda62c2294ad31215e0aed6 /Documentation/arm64/cpu-feature-registers.txt
parenta8ffaaa060b8d4da6138e0958cb0f45b73e1cb78 (diff)
downloadlwn-3b3b681097fae73b7f5dcdd42db6cfdf32943d4c.tar.gz
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arm64: v8.4: Support for new floating point multiplication instructions
ARM v8.4 extensions add new neon instructions for performing a multiplication of each FP16 element of one vector with the corresponding FP16 element of a second vector, and to add or subtract this without an intermediate rounding to the corresponding FP32 element in a third vector. This patch detects this feature and let the userspace know about it via a HWCAP bit and MRS emulation. Cc: Dave Martin <Dave.Martin@arm.com> Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Dongjiu Geng <gengdongjiu@huawei.com> Reviewed-by: Dave Martin <Dave.Martin@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Diffstat (limited to 'Documentation/arm64/cpu-feature-registers.txt')
-rw-r--r--Documentation/arm64/cpu-feature-registers.txt4
1 files changed, 3 insertions, 1 deletions
diff --git a/Documentation/arm64/cpu-feature-registers.txt b/Documentation/arm64/cpu-feature-registers.txt
index bd9b3faab2c4..a70090b28b07 100644
--- a/Documentation/arm64/cpu-feature-registers.txt
+++ b/Documentation/arm64/cpu-feature-registers.txt
@@ -110,7 +110,9 @@ infrastructure:
x--------------------------------------------------x
| Name | bits | visible |
|--------------------------------------------------|
- | RES0 | [63-48] | n |
+ | RES0 | [63-52] | n |
+ |--------------------------------------------------|
+ | FHM | [51-48] | y |
|--------------------------------------------------|
| DP | [47-44] | y |
|--------------------------------------------------|