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authorMarcelo Schmitt <marcelo.schmitt1@gmail.com>2019-03-16 12:07:32 -0300
committerJonathan Cameron <Jonathan.Cameron@huawei.com>2019-04-04 20:20:13 +0100
commita816646f08ce18e8787d241e1dbda5cbc314e5ea (patch)
tree31319c221e50aaba57b15f843fdc2b9a076f386f /Documentation/ABI
parent8fce3d34d70c98cd546cdb99365659087a408e02 (diff)
downloadlwn-a816646f08ce18e8787d241e1dbda5cbc314e5ea.tar.gz
lwn-a816646f08ce18e8787d241e1dbda5cbc314e5ea.zip
staging: iio: ad5933: add ABI documentation
Add an ABI documentation for the ad5933 driver. Signed-off-by: Marcelo Schmitt <marcelo.schmitt1@gmail.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Diffstat (limited to 'Documentation/ABI')
-rw-r--r--Documentation/ABI/testing/sysfs-bus-iio-impedance-analyzer-ad593335
1 files changed, 35 insertions, 0 deletions
diff --git a/Documentation/ABI/testing/sysfs-bus-iio-impedance-analyzer-ad5933 b/Documentation/ABI/testing/sysfs-bus-iio-impedance-analyzer-ad5933
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+What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency_start
+Date: March 2019
+KernelVersion: 3.1.0
+Contact: linux-iio@vger.kernel.org
+Description:
+ Frequency sweep start frequency in Hz.
+
+What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency_increment
+Date: March 2019
+KernelVersion: 3.1.0
+Contact: linux-iio@vger.kernel.org
+Description:
+ Frequency increment in Hz (step size) between consecutive
+ frequency points along the sweep.
+
+What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_frequency_points
+Date: March 2019
+KernelVersion: 3.1.0
+Contact: linux-iio@vger.kernel.org
+Description:
+ Number of frequency points (steps) in the frequency sweep.
+ This value, in conjunction with the
+ out_altvoltageY_frequency_start and the
+ out_altvoltageY_frequency_increment, determines the frequency
+ sweep range for the sweep operation.
+
+What: /sys/bus/iio/devices/iio:deviceX/out_altvoltageY_settling_cycles
+Date: March 2019
+KernelVersion: 3.1.0
+Contact: linux-iio@vger.kernel.org
+Description:
+ Number of output excitation cycles (settling time cycles)
+ that are allowed to pass through the unknown impedance,
+ after each frequency increment, and before the ADC is triggered
+ to perform a conversion sequence of the response signal.