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| author | Lu Baolu <baolu.lu@linux.intel.com> | 2019-11-20 14:10:16 +0800 |
|---|---|---|
| committer | Joerg Roedel <jroedel@suse.de> | 2019-12-18 16:18:34 +0100 |
| commit | f81b846dcd9a1e6d120f73970a9a98b7fcaaffba (patch) | |
| tree | b08f2a769d8053358f8582029a544cd733066fad | |
| parent | cde9319e884eb6267a0df446f3c131fe1108defb (diff) | |
| download | lwn-f81b846dcd9a1e6d120f73970a9a98b7fcaaffba.tar.gz lwn-f81b846dcd9a1e6d120f73970a9a98b7fcaaffba.zip | |
iommu/vt-d: Remove incorrect PSI capability check
The PSI (Page Selective Invalidation) bit in the capability register
is only valid for second-level translation. Intel IOMMU supporting
scalable mode must support page/address selective IOTLB invalidation
for first-level translation. Remove the PSI capability check in SVA
cache invalidation code.
Fixes: 8744daf4b0699 ("iommu/vt-d: Remove global page flush support")
Cc: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
| -rw-r--r-- | drivers/iommu/intel-svm.c | 6 |
1 files changed, 1 insertions, 5 deletions
diff --git a/drivers/iommu/intel-svm.c b/drivers/iommu/intel-svm.c index 9b159132405d..dca88f9fdf29 100644 --- a/drivers/iommu/intel-svm.c +++ b/drivers/iommu/intel-svm.c @@ -104,11 +104,7 @@ static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_d { struct qi_desc desc; - /* - * Do PASID granu IOTLB invalidation if page selective capability is - * not available. - */ - if (pages == -1 || !cap_pgsel_inv(svm->iommu->cap)) { + if (pages == -1) { desc.qw0 = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) | QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | |