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| author | Samuel Holland <samuel@sholland.org> | 2022-11-13 20:21:11 -0600 |
|---|---|---|
| committer | Vinod Koul <vkoul@kernel.org> | 2022-11-24 23:04:23 +0530 |
| commit | cb7f49a31597066b25c9bc6a0bf0781454dd4d2b (patch) | |
| tree | 97609e42ca4dec5b62abad5a21f4f17ccd07d5f4 | |
| parent | a709ae51e22802822de85ec7b672cf1cc5412fc0 (diff) | |
| download | lwn-cb7f49a31597066b25c9bc6a0bf0781454dd4d2b.tar.gz lwn-cb7f49a31597066b25c9bc6a0bf0781454dd4d2b.zip | |
phy: allwinner: phy-sun6i-mipi-dphy: Set the enable bit last
The A100 variant of the DPHY requires configuring the analog registers
before setting the global enable bit. Since this order also works on the
other variants, always use it, to minimize the differences between them.
Reviewed-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20221114022113.31694-7-samuel@sholland.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
| -rw-r--r-- | drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c index 7d7322670a83..a2afedc399fd 100644 --- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c +++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c @@ -183,10 +183,6 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) SUN6I_DPHY_TX_TIME4_HS_TX_ANA0(3) | SUN6I_DPHY_TX_TIME4_HS_TX_ANA1(3)); - regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, - SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) | - SUN6I_DPHY_GCTL_EN); - regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG, SUN6I_DPHY_ANA0_REG_PWS | SUN6I_DPHY_ANA0_REG_DMPC | @@ -244,6 +240,10 @@ static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy) SUN6I_DPHY_ANA2_EN_P2S_CPU_MASK, SUN6I_DPHY_ANA2_EN_P2S_CPU(lanes_mask)); + regmap_write(dphy->regs, SUN6I_DPHY_GCTL_REG, + SUN6I_DPHY_GCTL_LANE_NUM(dphy->config.lanes) | + SUN6I_DPHY_GCTL_EN); + return 0; } |