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authorPetr Machata <petrm@nvidia.com>2023-10-19 12:27:14 +0200
committerDavid S. Miller <davem@davemloft.net>2023-10-20 11:47:49 +0100
commit8eabd10cdce4fc30e4357eab1fd102530fb09275 (patch)
treebb6f824b0ddacbd20b856a33d542a12817e21dd3
parenteb26a59232770fc6137759965437ea55d067134b (diff)
downloadlwn-8eabd10cdce4fc30e4357eab1fd102530fb09275.tar.gz
lwn-8eabd10cdce4fc30e4357eab1fd102530fb09275.zip
mlxsw: cmd: Add QUERY_FW.lag_mode_support
Add QUERY_FW.lag_mode_support, which determines whether CONFIG_PROFILE.lag_mode is available. Signed-off-by: Petr Machata <petrm@nvidia.com> Reviewed-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: David S. Miller <davem@davemloft.net>
-rw-r--r--drivers/net/ethernet/mellanox/mlxsw/cmd.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/ethernet/mellanox/mlxsw/cmd.h b/drivers/net/ethernet/mellanox/mlxsw/cmd.h
index cb6e2a9ef03f..e827c78be114 100644
--- a/drivers/net/ethernet/mellanox/mlxsw/cmd.h
+++ b/drivers/net/ethernet/mellanox/mlxsw/cmd.h
@@ -276,6 +276,12 @@ MLXSW_ITEM32(cmd_mbox, query_fw, fw_month, 0x14, 8, 8);
*/
MLXSW_ITEM32(cmd_mbox, query_fw, fw_day, 0x14, 0, 8);
+/* cmd_mbox_query_fw_lag_mode_support
+ * 0: CONFIG_PROFILE.lag_mode is not supported by FW
+ * 1: CONFIG_PROFILE.lag_mode is supported by FW
+ */
+MLXSW_ITEM32(cmd_mbox, query_fw, lag_mode_support, 0x18, 1, 1);
+
/* cmd_mbox_query_fw_clr_int_base_offset
* Clear Interrupt register's offset from clr_int_bar register
* in PCI address space.