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| author | Biju Das <biju.das@bp.renesas.com> | 2018-04-20 16:27:07 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2018-04-25 08:51:02 +0200 |
| commit | 141fb10294e3ba5ee2d34d464ddc8a9952bd3372 (patch) | |
| tree | c7154e72847dd7481bc09aba806fe8c964069797 | |
| parent | 2e5775e3fd0667f7140a00748465af1c3d0aa5bb (diff) | |
| download | lwn-141fb10294e3ba5ee2d34d464ddc8a9952bd3372.tar.gz lwn-141fb10294e3ba5ee2d34d464ddc8a9952bd3372.zip | |
ARM: dts: r8a77470: Add IRQC support
Describe the IRQC interrupt controller in the R8A77470 device tree.
Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | arch/arm/boot/dts/r8a77470.dtsi | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/r8a77470.dtsi b/arch/arm/boot/dts/r8a77470.dtsi index c39acebc6a72..2f89f33f5b88 100644 --- a/arch/arm/boot/dts/r8a77470.dtsi +++ b/arch/arm/boot/dts/r8a77470.dtsi @@ -81,6 +81,26 @@ #power-domain-cells = <1>; }; + irqc: interrupt-controller@e61c0000 { + compatible = "renesas,irqc-r8a77470", "renesas,irqc"; + #interrupt-cells = <2>; + interrupt-controller; + reg = <0 0xe61c0000 0 0x200>; + interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 407>; + power-domains = <&sysc 32>; + resets = <&cpg 407>; + }; + icram0: sram@e63a0000 { compatible = "mmio-sram"; reg = <0 0xe63a0000 0 0x12000>; |