diff options
| author | Eugeni Dodonov <eugeni.dodonov@intel.com> | 2012-03-29 12:32:35 -0300 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2012-04-09 18:04:04 +0200 |
| commit | 90e8d31c53890064962f1154405e1034be7ec9a1 (patch) | |
| tree | 6306c85da1d7f710eba351264cc582e177cef527 | |
| parent | ccf1c867ce049bf27a1f7172f1a91820b3ceb6e5 (diff) | |
| download | lwn-90e8d31c53890064962f1154405e1034be7ec9a1.tar.gz lwn-90e8d31c53890064962f1154405e1034be7ec9a1.zip | |
drm/i915: add LCPLL control registers
Those are used to control the display core clock.
v2: change the enable bit setting, spotted by Rodrigo Vivi.
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5fe8e2dbef2d..8c44fe0b4fa4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4180,4 +4180,11 @@ #define PIPE_CLK_SEL_DISABLED (0x0<<29) #define PIPE_CLK_SEL_PORT(x) ((x+1)<<29) +/* LCPLL Control */ +#define LCPLL_CTL 0x130040 +#define LCPLL_PLL_DISABLE (1<<31) +#define LCPLL_PLL_LOCK (1<<30) +#define LCPLL_CD_CLOCK_DISABLE (1<<25) +#define LCPLL_CD2X_CLOCK_DISABLE (1<<23) + #endif /* _I915_REG_H_ */ |