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| author | Ville Syrjälä <ville.syrjala@linux.intel.com> | 2015-03-05 21:19:41 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2015-03-17 22:30:01 +0100 |
| commit | edf605601403194fdded0f8fd6305955d4ba009d (patch) | |
| tree | 8a2046e9ac133e17eadf682f6cecad826481016e | |
| parent | 48572edd9d736d6fabd40b810a0de844ee4f800b (diff) | |
| download | lwn-edf605601403194fdded0f8fd6305955d4ba009d.tar.gz lwn-edf605601403194fdded0f8fd6305955d4ba009d.zip | |
drm/i915: Reduce CHV DDL multiplier to 16/8
Apparently we must yet halve the DDL drain latency from what we're
using currently. This little nugget is not in any spec, but came
down through the grapevine.
This makes the displays a bit more stable. Not quite fully stable but at
least they don't fall over immediately on driver load.
v2: Update high_precision in valleyview_update_sprite_wm() too (Jesse)
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/intel_pm.c | 8 |
2 files changed, 5 insertions, 4 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 56b97c41bf17..1e5ce1bf56b1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4205,6 +4205,7 @@ enum skl_disp_power_wells { #define DSPFW_PLANEA_WM1_HI_MASK (1<<0) /* drain latency register values*/ +#define DRAIN_LATENCY_PRECISION_8 8 #define DRAIN_LATENCY_PRECISION_16 16 #define DRAIN_LATENCY_PRECISION_32 32 #define DRAIN_LATENCY_PRECISION_64 64 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index e2e8414d7151..94cc4b66bd89 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -756,8 +756,8 @@ static bool vlv_compute_drain_latency(struct drm_crtc *crtc, entries = DIV_ROUND_UP(clock, 1000) * pixel_size; if (IS_CHERRYVIEW(dev)) - *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 : - DRAIN_LATENCY_PRECISION_16; + *prec_mult = (entries > 32) ? DRAIN_LATENCY_PRECISION_16 : + DRAIN_LATENCY_PRECISION_8; else *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 : DRAIN_LATENCY_PRECISION_32; @@ -787,7 +787,7 @@ static void vlv_update_drain_latency(struct drm_crtc *crtc) enum pipe pipe = intel_crtc->pipe; int plane_prec, prec_mult, plane_dl; const int high_precision = IS_CHERRYVIEW(dev) ? - DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64; + DRAIN_LATENCY_PRECISION_16 : DRAIN_LATENCY_PRECISION_64; plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH | DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH | @@ -986,7 +986,7 @@ static void valleyview_update_sprite_wm(struct drm_plane *plane, int sprite_dl; int prec_mult; const int high_precision = IS_CHERRYVIEW(dev) ? - DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64; + DRAIN_LATENCY_PRECISION_16 : DRAIN_LATENCY_PRECISION_64; sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) | (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite))); |