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authorMichel Dänzer <michel.daenzer@amd.com>2015-11-05 17:25:27 +0900
committerSasha Levin <sasha.levin@oracle.com>2016-02-15 15:45:31 -0500
commit5e92a4058e7035fde9a623b5ca36d862e7677ea6 (patch)
tree4d22b1296e3a4e673a0027583e2040f623e80e16
parent2322974c5d55e8be4be4b7cbf8cf996daf72b0bd (diff)
downloadlwn-5e92a4058e7035fde9a623b5ca36d862e7677ea6.tar.gz
lwn-5e92a4058e7035fde9a623b5ca36d862e7677ea6.zip
drm/radeon: Always disable RADEON_GEM_GTT_UC along with RADEON_GEM_GTT_WC
[ Upstream commit a28bbd5824d4a2af98de45b300ab8d8fb39739fc ] Write-combining is a CPU feature. From the GPU POV, these both simply mean no GPU<->CPU cache coherency. Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Michel Dänzer <michel.daenzer@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
-rw-r--r--drivers/gpu/drm/radeon/radeon_object.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_object.c b/drivers/gpu/drm/radeon/radeon_object.c
index 676362769b8d..c12eea5e5875 100644
--- a/drivers/gpu/drm/radeon/radeon_object.c
+++ b/drivers/gpu/drm/radeon/radeon_object.c
@@ -225,7 +225,7 @@ int radeon_bo_create(struct radeon_device *rdev,
/* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
* See https://bugs.freedesktop.org/show_bug.cgi?id=84627
*/
- bo->flags &= ~RADEON_GEM_GTT_WC;
+ bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
#elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
/* Don't try to enable write-combining when it can't work, or things
* may be slow
@@ -237,7 +237,7 @@ int radeon_bo_create(struct radeon_device *rdev,
DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
"better performance thanks to write-combining\n");
- bo->flags &= ~RADEON_GEM_GTT_WC;
+ bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
#endif
radeon_ttm_placement_from_domain(bo, domain);