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| author | Stephen Warren <swarren@nvidia.com> | 2015-02-24 14:00:50 -0700 |
|---|---|---|
| committer | Linus Walleij <linus.walleij@linaro.org> | 2015-03-09 18:10:58 +0100 |
| commit | ec654e50c67ad4ba89c9f9f81ccf6f061695e36d (patch) | |
| tree | 33c64165564ab3d5935b61e36c1bdeb9cdec93d0 | |
| parent | ea623061930ccf6d37b4a09a4e65a26fcf552c22 (diff) | |
| download | lwn-ec654e50c67ad4ba89c9f9f81ccf6f061695e36d.tar.gz lwn-ec654e50c67ad4ba89c9f9f81ccf6f061695e36d.zip | |
pinctrl: tegra: support nvidia,io-hv DT property
Both nvidia,io-hv and nvidia,rcv-sel represent the fact that a particular
pin's IO buffers are configured to accept "high voltage" input signals.
The TRM for different chips names the register field rcv-sel on older
SoCs and io_hv on newer SoCs. Add the new naming option into the pinctrl
driver so that DT files can use naming consistent with the TRM.
This new property name will be documented in the patch that adds support
for the new SoC.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
| -rw-r--r-- | drivers/pinctrl/pinctrl-tegra.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c index 6cd651a88398..4c95c2024a1c 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c @@ -103,6 +103,7 @@ static const struct cfg_param { {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK}, {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET}, {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL}, + {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL}, {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE}, {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT}, {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE}, |