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authorAlex Deucher <alexander.deucher@amd.com>2012-08-06 17:06:03 -0400
committerBen Hutchings <ben@decadent.org.uk>2012-09-19 15:05:23 +0100
commitca9d5df1dce289bf297c94d6e3fa5afa01885146 (patch)
tree35ba51dfa740a96130687064340a72c0c7fc8ab0
parent540e00f8662500ff2b6289871b4ca919cd9d6a21 (diff)
downloadlwn-ca9d5df1dce289bf297c94d6e3fa5afa01885146.tar.gz
lwn-ca9d5df1dce289bf297c94d6e3fa5afa01885146.zip
drm/radeon: fix ordering in pll picking on dce4+
commit ecd67955fd4c8e66e4df312098989d5fa7da624c upstream. No functional change, but re-order the cases so they evaluate properly due to the way the DCE macros work. Noticed by kallisti5 on IRC. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> [bwh: Backported to 3.2: drop the DCE6 case] Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index ccabbc546ded..a4011b0bd3e4 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1468,10 +1468,10 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
* crtc virtual pixel clock.
*/
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
- if (ASIC_IS_DCE5(rdev))
- return ATOM_DCPLL;
- else if (rdev->clock.dp_extclk)
+ if (rdev->clock.dp_extclk)
return ATOM_PPLL_INVALID;
+ else if (ASIC_IS_DCE5(rdev))
+ return ATOM_DCPLL;
}
}
}