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authorAlex Deucher <alexander.deucher@amd.com>2012-07-17 14:02:43 -0400
committerBen Hutchings <ben@decadent.org.uk>2012-09-19 15:05:22 +0100
commit540e00f8662500ff2b6289871b4ca919cd9d6a21 (patch)
tree2afdfa02542b892897dfd062ab96269cd7c774cc
parentb7e804af32be49d07d2386ae6a977984124ad8f6 (diff)
downloadlwn-540e00f8662500ff2b6289871b4ca919cd9d6a21.tar.gz
lwn-540e00f8662500ff2b6289871b4ca919cd9d6a21.zip
drm/radeon: fix up pll selection on DCE5/6
commit 26fe45a0a76f165425f332a5aaa298f149f9db22 upstream. Selecting ATOM_PPLL_INVALID should be equivalent as the DCPLL or PPLL0 are already programmed for the DISPCLK, but the preferred method is to always specify the PLL selected. SetPixelClock will check the parameters and skip the programming if the PLL is already set up. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> [bwh: Backported to 3.2: drop the DCE6 case] Signed-off-by: Ben Hutchings <ben@decadent.org.uk>
-rw-r--r--drivers/gpu/drm/radeon/atombios_crtc.c4
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 40bd6562f321..ccabbc546ded 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1468,7 +1468,9 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
* crtc virtual pixel clock.
*/
if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
- if (ASIC_IS_DCE5(rdev) || rdev->clock.dp_extclk)
+ if (ASIC_IS_DCE5(rdev))
+ return ATOM_DCPLL;
+ else if (rdev->clock.dp_extclk)
return ATOM_PPLL_INVALID;
}
}