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| author | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-05-03 11:49:51 +0200 |
|---|---|---|
| committer | Daniel Vetter <daniel.vetter@ffwll.ch> | 2013-05-06 11:23:46 +0200 |
| commit | 4d8a62eac3caad710ef030aab25248d56693a8f1 (patch) | |
| tree | 05e92d2ea67564ca0696ab7448337ddcc96cb77d | |
| parent | 0e50e96bf2d89c3415cb68aead301f485938f1ca (diff) | |
| download | lwn-4d8a62eac3caad710ef030aab25248d56693a8f1.tar.gz lwn-4d8a62eac3caad710ef030aab25248d56693a8f1.zip | |
drm/i915: fix up adjusted_mode tracking for interlaced modes
With the hw state readout&check code it's important that the values we
keep around are the canonical ones. Unfortunately when adding the pipe
timings readout support I've missed that the write side adjusts the
timings in the pipe config.
Fix this up and so prevent the unsightly WARN noise in dmesg. This
regression has been introduced in
commit 1bd1bd806037af04dd1d7bdd39b2b04090c10d2c
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Mon Apr 29 21:56:12 2013 +0200
drm/i915: hw state readout support for pipe timings
Reported-by: Paulo Zanoni <przanoni@gmail.com>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Tested-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 15 |
1 files changed, 10 insertions, 5 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index de8be7595a62..3a691a13f9e6 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -4675,12 +4675,17 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, struct drm_i915_private *dev_priv = dev->dev_private; enum pipe pipe = intel_crtc->pipe; enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; - uint32_t vsyncshift; + uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end; + + /* We need to be careful not to changed the adjusted mode, for otherwise + * the hw state checker will get angry at the mismatch. */ + crtc_vtotal = adjusted_mode->crtc_vtotal; + crtc_vblank_end = adjusted_mode->crtc_vblank_end; if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { /* the chip adds 2 halflines automatically */ - adjusted_mode->crtc_vtotal -= 1; - adjusted_mode->crtc_vblank_end -= 1; + crtc_vtotal -= 1; + crtc_vblank_end -= 1; vsyncshift = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_htotal / 2; } else { @@ -4702,10 +4707,10 @@ static void intel_set_pipe_timings(struct intel_crtc *intel_crtc, I915_WRITE(VTOTAL(cpu_transcoder), (adjusted_mode->crtc_vdisplay - 1) | - ((adjusted_mode->crtc_vtotal - 1) << 16)); + ((crtc_vtotal - 1) << 16)); I915_WRITE(VBLANK(cpu_transcoder), (adjusted_mode->crtc_vblank_start - 1) | - ((adjusted_mode->crtc_vblank_end - 1) << 16)); + ((crtc_vblank_end - 1) << 16)); I915_WRITE(VSYNC(cpu_transcoder), (adjusted_mode->crtc_vsync_start - 1) | ((adjusted_mode->crtc_vsync_end - 1) << 16)); |