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| author | Ben Dooks <ben-linux@fluff.org> | 2009-02-20 20:33:08 +0300 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@suse.de> | 2009-03-16 17:32:28 -0700 |
| commit | 8cce128ef6e1d3cefca3cedf34ee5415e100d429 (patch) | |
| tree | c4846ca0382a06dfb414c58c42946d1340f95ce7 | |
| parent | 8a36a1251e3be6a07976c186c6aee160be84b40c (diff) | |
| download | lwn-8cce128ef6e1d3cefca3cedf34ee5415e100d429.tar.gz lwn-8cce128ef6e1d3cefca3cedf34ee5415e100d429.zip | |
sdhci: Add quirk for controllers with no end-of-busy IRQ
commit f945405cdecd9e0ae3e58ff84cabd19b4522965e upstream.
The Samsung SDHCI (and FSL eSDHC) controller block seems to fail
to generate an INT_DATA_END after the transfer has completed and
the bus busy state finished.
Changes in e809517f6fa5803a5a1cd56026f0e2190fc13d5c to use the
new busy method are the cause of the behaviour change.
Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Pierre Ossman <drzeus@drzeus.cx>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| -rw-r--r-- | drivers/mmc/host/sdhci.c | 5 | ||||
| -rw-r--r-- | drivers/mmc/host/sdhci.h | 2 |
2 files changed, 6 insertions, 1 deletions
diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 59166588275f..b4f6b3ce0c03 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -1286,8 +1286,11 @@ static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask) if (host->cmd->data) DBG("Cannot wait for busy signal when also " "doing a data transfer"); - else + else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ)) return; + + /* The controller does not support the end-of-busy IRQ, + * fall through and take the SDHCI_INT_RESPONSE */ } if (intmask & SDHCI_INT_RESPONSE) diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 6a11adfc7604..04c02ac4d747 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -210,6 +210,8 @@ struct sdhci_host { #define SDHCI_QUIRK_BROKEN_SMALL_PIO (1<<13) /* Controller supports high speed but doesn't have the caps bit set */ #define SDHCI_QUIRK_FORCE_HIGHSPEED (1<<14) +/* Controller does not provide transfer-complete interrupt when not busy */ +#define SDHCI_QUIRK_NO_BUSY_IRQ (1<<15) int irq; /* Device IRQ */ void __iomem * ioaddr; /* Mapped address */ |