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authorDarrick J. Wong <djwong@us.ibm.com>2010-06-30 17:45:19 -0700
committerGreg Kroah-Hartman <gregkh@suse.de>2010-08-02 10:18:51 -0700
commit34883b011409464e6b0cf0b52a54e6b0503bd06f (patch)
tree9f7407b414c218f84a4e6282087e246dec678145
parent6e992ba3c5662c42cb3b555fdf67e4dd4dcac84c (diff)
downloadlwn-34883b011409464e6b0cf0b52a54e6b0503bd06f.tar.gz
lwn-34883b011409464e6b0cf0b52a54e6b0503bd06f.zip
x86, Calgary: Limit the max PHB number to 256
commit d596043d71ff0d7b3d0bead19b1d68c55f003093 upstream. The x3950 family can have as many as 256 PCI buses in a single system, so change the limits to the maximum. Since there can only be 256 PCI buses in one domain, we no longer need the BUG_ON check. Signed-off-by: Darrick J. Wong <djwong@us.ibm.com> LKML-Reference: <20100701004519.GQ15515@tux1.beaverton.ibm.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--arch/x86/kernel/pci-calgary_64.c4
1 files changed, 1 insertions, 3 deletions
diff --git a/arch/x86/kernel/pci-calgary_64.c b/arch/x86/kernel/pci-calgary_64.c
index 90bc1c32fdd9..d8a4dc6c3d65 100644
--- a/arch/x86/kernel/pci-calgary_64.c
+++ b/arch/x86/kernel/pci-calgary_64.c
@@ -109,7 +109,7 @@ int use_calgary __read_mostly = 0;
* x3950 (PCIE): 8 chassis, 32 PHBs per chassis = 256
* x3950 (PCIX): 8 chassis, 16 PHBs per chassis = 128
*/
-#define MAX_PHB_BUS_NUM 384
+#define MAX_PHB_BUS_NUM 256
#define PHBS_PER_CALGARY 4
@@ -1097,8 +1097,6 @@ static int __init calgary_init_one(struct pci_dev *dev)
struct iommu_table *tbl;
int ret;
- BUG_ON(dev->bus->number >= MAX_PHB_BUS_NUM);
-
bbar = busno_to_bbar(dev->bus->number);
ret = calgary_setup_tar(dev, bbar);
if (ret)