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authorArjan van de Ven <arjan@linux.intel.com>2006-12-11 21:45:01 +0100
committerChris Wright <chrisw@sous-sol.org>2007-01-10 11:05:17 -0800
commit33e57a8e59504540ad5a6070dd1b70493cc68024 (patch)
treeebfb39b1a5e6bc781f4fa7620cf2ab7f2b35cf32
parent4ad328ffdcf3d014ff98ff75afcf457387c8bd56 (diff)
downloadlwn-33e57a8e59504540ad5a6070dd1b70493cc68024.tar.gz
lwn-33e57a8e59504540ad5a6070dd1b70493cc68024.zip
[PATCH] x86-64: Mark rdtsc as sync only for netburst, not for core2
On the Core2 cpus, the rdtsc instruction is not serializing (as defined in the architecture reference since rdtsc exists) and due to the deep speculation of these cores, it's possible that you can observe time go backwards between cores due to this speculation. Since the kernel already deals with this with the SYNC_RDTSC flag, the solution is simple, only assume that the instruction is serializing on family 15... The price one pays for this is a slightly slower gettimeofday (by a dozen or two cycles), but that increase is quite small to pay for a really-going-forward tsc counter. Signed-off-by: Arjan van de Ven <arjan@linux.intel.com> Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Chris Wright <chrisw@sous-sol.org>
-rw-r--r--arch/x86_64/kernel/setup.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/x86_64/kernel/setup.c b/arch/x86_64/kernel/setup.c
index fc944b5e8f4a..013539fa53f0 100644
--- a/arch/x86_64/kernel/setup.c
+++ b/arch/x86_64/kernel/setup.c
@@ -854,7 +854,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
set_bit(X86_FEATURE_CONSTANT_TSC, &c->x86_capability);
if (c->x86 == 6)
set_bit(X86_FEATURE_REP_GOOD, &c->x86_capability);
- set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
+ if (c->x86 == 15)
+ set_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
+ else
+ clear_bit(X86_FEATURE_SYNC_RDTSC, &c->x86_capability);
c->x86_max_cores = intel_num_cpu_cores(c);
srat_detect_node();